1. Field of the Invention
The present invention generally relates to serial access memory devices, and more particularly, to a serial access device capable of controlling order of access to memory cell areas. The present invention has particular applicability to a progressive scan conversion circuit and an RGB line memory device for video signal processing.
2. Description of the Related Art
In recent years, semiconductor memory devices have come to be applied to a variety of electronic equipment. Correspondingly, there is an increasing demand not only for general-purpose semiconductor memory devices but for those suited to video signal processing or picture processing for example. Therefore, in order to perform video signal processing or picture processing, a semiconductor memory device capable of serially inputting/outputting data signals that constitute a video image or picture ("serial access memory device") is required.
FIG. 1 is a block diagram of a conventional serial access memory device. Referring to the diagram, this memory device comprises a memory cell array 1 including memory cells of n bits by k rows by m columns, a writing row selecting circuit 2 for serially selecting a row in the memory cell array 1 to which data are to be written, a reading row selecting circuit 3 for serially selecting a row in the memory cell array 1 from which data are to be read out, writing column selecting circuit 4 for serially selecting a column in the memory cell array 1 to which data are to be written, and a reading column selecting circuit 5 for serially selecting a column in the memory cell array 1 from which data are to be read out. These selecting circuit 2, 3, 4 and 5 are generally constituted of ring pointer circuits.
An n-bit input data bus 6 is connected to the memory cell array 1 through an input bus selector circuit. The input data bus 6 has n input data lines. The n input data lines supply n-bit input data in parallel to each column provided in the memory cell array 1. In the writing operation, the thus supplied n-bit input data are written in memory cells disposed in the row selected by the writing row selecting circuit 2 and in the column selected by the writing column selecting circuit 4.
An output data bus 7 is connected to the memory cell array 1 through an output bus selector circuit. The output data bus 7 has n output data lines. The output data bus 7 is connected to the memory cell array 1 to receive n-bit data read out from each column in the memory cell array 1. In the reading operation, n-bit data are read out from memory cells in the row selected by the reading row selecting circuit 3 and in the column selected by the reading column selecting circuit 5 and then applied to the output data bus 7.
Addressing for a writing operation is reset in response to an externally applied write reset signal WRST. After the writing address has been reset, the first column is selected by the writing column selecting circuit 4. One of the rows in the selected first column is selected, in response to a writing clock signal WCLK, serially, allowing data on the input data bus 6 to be written therein. The writing column selecting circuit 4 serially selects one of the columns in the memory cell array 1. When the last m-th column is selected by the writing column selecting circuit 4, the first column is selected again. Thereafter, the column and row selection for the writing is repeated, whereby data on the input data bus 6 for the writing are serially written in the memory cell array 1.
The writing row selecting circuit 2 and the writing column selecting circuit 4 select, in response to the writing clock signal WCLK, a row and a column for the writing. Similarly, the reading row selecting circuit 3 and the reading column selecting circuit 5 select, in response to a reading clock signal RCLK, a row and a column in the memory cell array 1 from which data are to be read out. From the memory cells of the selected row and column, data that have been stored therein are serially read out and applied to the output data bus 7.
Assuming now that the memory cell array 1 shown in FIG. 1 has a circuit structure of n=8, k=182 and m=5, this serial access memory device can be applied to an asynchronous line memory in an NTSC color television for video signal processing.
FIG. 2 is a block diagram of a progressive scan conversion circuit for video signal processing, using two of the serial access memory device shown in FIG. 1. Referring to the diagram, this progressive scan conversion circuit comprises two serial access memory devices 81 and 82 provided on a single semiconductor chip. Each of the memory devices 81 and 82 is connected to receive the writing clock signal WCLK, the reading clock signal RCLK, the writing reset signal WRST and a reading reset signal RRST. The memory device 81 is connected to receive video signals with its data input DI. The memory device 82 is connected to receive line interpolating signals with its data input DI. A switching circuit 10 is connected between data outputs DOs of the memory devices 81 and 82. Video signals that have been doubled in speed (or converted for progressive, rather than interlaced, scan) are outputted through the switching circuit 10. Another switching circuit 9 supplies the reading clock signal RCLK to the memory devices 81 and 82 alternately.
The "progressive scan conversion" is required to double the number of scanning lines in one field. Accordingly, the writing clock signal WCLK has a frequency of 14.3 MHz (equivalent to fourfold the color subcarrier frequency f.sub.SC). The serial access memory device 81 is responsive to the clock signal WCLK for receiving an A/D-converted 8-bit video signal. The serial access memory device 82 is responsive to the clock signal WCLK for receiving a line interpolating signal. After the writing is effected on over half of all the data (455 samples), data stored in the memory devices 81 and 82 are alternately read out, based on switching control by the switching circuits 9 and 10. The reading clock signal RCLK has a frequency of twice that of the writing clock signal WCLK, or 28.6 MHz. The reading clock signal RCLK is supplied to the memory devices 81 and 82 alternately through the switching circuit 9 so that those data read out from the memory devices 81 and 82 are outputted through the switching circuit 10 as signals converted for progressive scan.
As described above, a conventional progressive scan conversion circuit for video signal processing requires two serial access memory devices. Accordingly, the total memory capacity required in the memory devices 81 and 82 is increased. In addition, it is to be noted that non-preparedness of any redundancy circuit leads to a low yield. Therefore, if only one memory cell has any defect for example, the whole memory device will be inevitably regarded as a defective. This results in a decreased productive efficiency.
Furthermore, since the switching circuits 9 and 10 are required for control of the two memory devices 81 and 82, control of these switching circuits 9 and 10 and the whole circuit structure are complicated. It has been pointed out that these inconveniences result from functional inflexibility of the serial access memory device shown in FIG. 1 in which order of access is fixed in advance.